Emanuel Berg writes:

Radey Shouman wrote:

the much deeper instruction pipelines

"deeper instruction pipelines", is that like
the many transformations of graphical data
before it appears on the screen, or a shell
parsing of a text string with UNIX tools,
i.e. done_value=$(a | b | ... | n) ? If so, are
the extra steps because of new capabilities the
CPU has that wasn't there before?

Only very approximately. A pipelined processor speculatively begins
executing one instruction before the previous one has finished. Each
instruction requires a sequence of steps: fetching the instruction from
cache, decoding, fetching the operands, doing the operation, storing to
destination ... The processor I am writing for at the moment has an 8
stage pipeline, meaning that an instruction that might have taken 8
cycles to execute in the stone ages of computing, when John and Tom were
still carrying lunchboxes, might execute in only one cycle, *if*
everything goes smoothly.

Often things do not go smoothly, for example, some earlier instruction
might modify a value needed as an operand for a later instruction,
causing a pipeline stall. Obviously branches are a disaster -- modern
processors try to predict which branch will be taken, and continue
speculative execution there. Some processors allow instructions to live
in one or more "delay slots", and are unconditionally executed after a
branch regardless of whether it is taken or not.

Back in the day you could just look up the number of cycles required by
your instructions, add them up, and know how long some operation would
take. Not any more, now you have to either try it, or use a
cycle-accurate simulator.


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